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CD4502BMS
December 1992
CMOS Strobed Hex Inverter/Buffer
Pinout
CD4502BMS TOP VIEW
Features
* High Voltage Type (20V Rating) * 2 TTL Load Output Drive Capability * 3 State Outputs * Common Output Disable Control * Inhibit Control * 100% Tested for Quiescent Current at 20V * 5V, 10V and 15V Parametric Ratings * Maximum Input Current of 1A at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC * Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V * Meets All Requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of `B' Series CMOS Devices"
D3 Q3 D1
1 2 3
16 VDD 15 D6 14 Q6 13 D5 12 INHIBIT 11 Q5 10 D4 9 Q4
3 STATE 4 OUTPUT DISABLE Q1 5 D2 Q2 VSS 6 7 8
Functional Diagram
3 STATE 4 OUTPUT DISABLE 12 INHIBIT 3 D1 D2 6
Applications
* 3 State Hex Inverter for Interfacing ICs with Data Buses * COS/MOS to TTL Hex Buffer
5 7
Q1 Q2
Description
CD4502BMS consists of six inverter/buffers with 3 state outputs. A logic "1" on the OUTPUT DISABLE input produces a high impedance state in all six outputs. This feature permits common busing of the outputs, thus simplifying system design. A Logic "1" on the INHIBIT input switches all six outputs to logic "0" if the OUTPUT DISABLE input is a logic "0". This device is capable of driving two standard TTL loads, which is equivalent to six times the JEDEC "B" series IOL standard. The CD4502BMS is supplied in these 16-lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack H4T H1F H6W
D3
1
2
Q3
D4
10
9
Q4
D5
13
11
Q5
D6
15
14
Q6
VDD = 16 VSS = 8
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999
File Number
3334
7-473
Specifications CD4502BMS
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 1/32 Inch (1.59mm 0.79mm) from case for 10s Maximum
Reliability Information
Thermal Resistance . . . . . . . . . . . . . . . . ja jc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2 VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 VDD = 18V Output Voltage Output Voltage Output Current (Sink) Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) N Threshold Voltage P Threshold Voltage Functional VOL15 VOH15 IOL5 IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VNTH VPTH F VDD = 15V, No Load VDD = 15V, No Load (Note 3) VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD = 15V, VOUT = 13.5V VDD = 10V, ISS = -10A VSS = 0V, IDD = 10A VDD = 2.8V, VIN = VDD or GND VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Input Voltage Low (Note 2) Input Voltage High (Note 2) Input Voltage Low (Note 2) Input Voltage High (Note 2) Tri-State Output Leakage VIL5 VIH5 VIL15 VIH15 IOZL VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V VIN = VDD or GND VOUT = 0V VDD = 20V VDD = 18V Tri-State Output Leakage IOZH VIN = VDD or GND VOUT = VDD VDD = 20V VDD = 18V NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. 3 1 2 3 1 2 3 1, 2, 3 1, 2, 3 1 1 1 1 1 1 1 1 1 7 7 8A 8B 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1 2 3 1 2 3 +25oC, LIMITS TEMPERATURE +25oC +125 C -55oC +25oC +125oC -55oC +25oC +125oC -55oC +125oC, +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +125oC -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC +125oC -55oC +25oC +125oC -55oC 3.5 11 -0.4 -12 -0.4 1.5 4 0.4 12 0.4 V V V V A A A A A A -55oC
o
PARAMETER Supply Current
SYMBOL IDD
CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND
MIN -100 -1000 -100 3.06 7.8 20.4 -2.8 0.7
MAX 2 200 2 100 1000 100 50 -0.53 -1.8 -1.4 -3.5 -0.7 2.8
UNITS A A A nA nA nA nA nA nA mV V mA mA mA mA mA mA mA V V V
+25oC, +125oC, -55oC 14.95
VOH > VOL < VDD/2 VDD/2
3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max.
7-474
Specifications CD4502BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS TEMPERATURE 9 10, 11 9 10, 11 9 10, 11 9 10, 11 9 10, 11 9 10, 11 9 10, 11 9 10, 11 9 10, 11 9 10, 11 +25oC +125oC, -55oC LIMITS MIN MAX 270 365 380 513 270 365 380 513 120 162 220 297 250 338 250 338 120 162 200 270 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
PARAMETER Propagation Delay Data or Inhibit to Output Propagation Delay Data or Inhibit to Output Propagation Delay Inhibit to Output Propagation Delay Inhibit to Output Propagation Delay Disable to Output Propagation Delay Disable to Output Propagation Delay Disable to Output Propagation Delay Disable to Output Transition Time
SYMBOL TPHL1
CONDITIONS VDD = 5V, VIN = VDD or GND (Note 1, 2) VDD = 5V, VIN = VDD or GND (Note 1, 2) VDD = 5V, VIN = VDD or GND (Note 1, 2) VDD = 5V, VIN = VDD or GND (Note 1, 2) VDD = 5V, VIN = VDD or GND (Note 2, 3) VDD = 5V, VIN = VDD or GND (Note 2, 3) VDD = 5V, VIN = VDD or GND (Note 2, 3) VDD = 5V, VIN = VDD or GND (Note 2, 3) VDD = 5V, VIN = VDD or GND (Note 1, 2) VDD = 5V, VIN = VDD or GND (Note 1, 2)
TPLH1
+25oC +125oC, -55oC
TPHL2
+25oC +125oC, -55oC
TPLH2
+25oC +125oC, -55oC
TPHZ
+25oC +125oC, -55oC
TPZH
+25oC +125oC, -55oC
TPLZ
+25oC +125oC, -55oC
TPZL
+25oC +125oC, -55oC
TTHL
+25oC +125oC, -55oC
Transition Time
TTLH
+25oC +125oC, -55oC
NOTES: 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. 3. VDD = 5V, CL = 50pF, RL = 1K, Input TR, TF < 20ns. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS VDD = 5V, VIN = VDD or GND NOTES 1, 2 TEMPERATURE -55oC, -55oC, -55oC, +25oC +25oC +25oC +125oC VDD = 10V, VIN = VDD or GND 1, 2 +125oC VDD = 15V, VIN = VDD or GND 1, 2 +125oC Output Voltage Output Voltage Output Voltage Output Voltage Output Current (Sink) VOL VOL VOH VOH IOL5 VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, VOUT = 0.4V 1, 2 1, 2 1, 2 1, 2 1, 2 +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +125oC -55oC 4.95 9.95 2.16 3.84 50 mV V V mA mA MIN MAX 1 30 2 60 2 120 50 UNITS A A A A A A mV
7-475
Specifications CD4502BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Output Current (Sink) SYMBOL IOL10 CONDITIONS VDD = 10V, VOUT = 0.5V NOTES 1, 2, 4 TEMPERATURE +125oC -55oC Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2, 4 +125oC -55oC Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC -55oC Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC -55oC Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125 C -55oC Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC -55oC Input Voltage Low Input Voltage High Propagation Delay Data to Output Propagation Delay Data to Output Propagation Delay Inhibit to Output Propagation Delay Inhibit to Output Propagation Delay Disable to Output Propagation Delay Disable to Output Propagation Delay Disable to Output Propagation Delay Disable to Output Transition Time VIL VIH TPHL1 VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V VDD = 15V TPLH1 VDD = 10V VDD = 15V TPHL2 VDD = 10V VDD = 15V TPLH2 VDD = 10V VDD = 15V TPHZ VDD = 10V VDD = 15V TPZH VDD = 10V VDD = 15V TPLZ VDD = 10V VDD = 15V TPZL VDD = 10V VDD = 15V TTHL VDD = 10V VDD = 15V Transition Time TTLH VDD = 10V VDD = 15V Input Capacitance NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. CL = 50pF, RL = 1K, Input TR, TF < 20ns. CIN Any Inputs 1, 2 1, 2 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2 +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC
o
MIN 5.4 9.6 14.4 25.2 +7 -
MAX -0.36 -0.64 -1.15 -2.0 -0.9 -1.6 -2.4 -4.2 3 120 80 180 130 120 80 180 130 80 60 100 80 130 110 110 80 60 40 100 80 7.5
UNITS mA mA mA mA mA mA mA mA mA mA mA mA V V ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF
7-476
Specifications CD4502BMS
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current N Threshold Voltage N Threshold Voltage Delta P Threshold Voltage P Threshold Voltage Delta Functional SYMBOL IDD VNTH VTN VTP VTP F CONDITIONS VDD = 20V, VIN = VDD or GND VDD = 10V, ISS = -10A VDD = 10V, ISS = -10A VSS = 0V, IDD = 10A VSS = 0V, IDD = 10A VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 1, 2, 3, 4 +25oC NOTES 1, 4 1, 4 1, 4 1, 4 1, 4 1 TEMPERATURE +25oC +25oC +25oC +25oC +25oC +25oC MIN -2.8 0.2 VOH > VDD/2 MAX 7.5 -0.2 1 2.8 1 VOL < VDD/2 1.35 x +25oC Limit UNITS A V V V V V
ns
NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
3. See Table 2 for +25oC limit. 4. Read and Record
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC PARAMETER Supply Current - MSI-1 Output Current (Sink) Output Current (Source) SYMBOL IDD IOL5 IOH5A 0.2A 20% x Pre-Test Reading 20% x Pre-Test Reading DELTA LIMIT
TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP Initial Test (Pre Burn-In) Interim Test 1 (Post Burn-In) Interim Test 2 (Post Burn-In) PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group A Group B Subgroup B-5 Subgroup B-6 Group D MIL-STD-883 METHOD 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 Sample 5005 Sample 5005 Sample 5005 Sample 5005 GROUP A SUBGROUPS 1, 7, 9 1, 7, 9 1, 7, 9 1, 7, 9, Deltas 1, 7, 9 1, 7, 9, Deltas 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas 1, 7, 9 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3 Subgroups 1, 2, 3, 9, 10, 11 IDD, IOL5, IOH5A READ AND RECORD IDD, IOL5, IOH5A IDD, IOL5, IOH5A IDD, IOL5, IOH5A
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION MIL-STD-883 METHOD 5005 TEST PRE-IRRAD 1, 7, 9 POST-IRRAD Table 4 READ AND RECORD PRE-IRRAD 1, 9 POST-IRRAD Table 4
CONFORMANCE GROUPS Group E Subgroup 2
7-477
Specifications CD4502BMS
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION Static Burn-In 1 Note 1 Static Burn-In 2 Note 1 Dynamic BurnIn Note 1 Irradiation Note 2 NOTES: 1. Each pin except VDD and GND will have a series resistor of 10K 5%, VDD = 18V 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V 0.5V OPEN 2, 5, 7, 9, 11, 14 2, 5, 7, 9, 11, 14 2, 5, 7, 9, 11, 14 GROUND 1, 3, 4, 6, 8, 10, 12, 13, 15 8 8 8 VDD 16 1, 3, 4, 6, 10, 12, 13, 15, 16 16 1, 3, 4, 6, 10, 12, 13, 15, 16 2, 5, 7, 9, 11, 14 4 1, 3, 6, 10, 12, 13, 15 9V -0.5V 50kHz 25kHz
Logic Diagram
INVERTER/BUFFER NO. 1 DI * 3-STATE OUTPUT * DISABLE INHIBIT * VSS VDD
TRUTH TABLE DISABLE
Q1
INHIBIT 0 0 1 X
Dn 0 1 X X
Qn 1 0 0 Z
0 0 0 1
TO 5 OTHER INVERTER/BUFFERS
VDD
Logic 0 = Low Logic 1 = High Z = High Impedance X = Don't Care
VSS
* ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION NETWORK
FIGURE 1. LOGIC DIAGRAM OF 1 OF 6 IDENTICAL INVERTER/BUFFERS
Test Circuit and Waveform
VDD D3 Q3 D1 PULSE GENERATOR DISABLE Q1 D2 Q2 VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD D6 Q6 D5 INHIBIT Q5 D4 Q4 tPLZ 10% tPZL 90% 50% 50% 1k A CL 0.01kF
VDD VOL VOH
TEST CONDITIONS TEST tPHZ tPLZ tPZL tPZH PIN 15 VSS VDD VDD VSS POINT A VSS VDD VDD VSS
tPHZ 10% tPZH 90%
VSS
FIGURE 2. DISABLE DELAY TIMES TEST CIRCUIT AND WAVEFORMS
7-478
Typical Performance Characteristics
1/6 OUTPUT LOW (SINK) CURRENT (IOL) (mA) 1/6 OUTPUT LOW (SINK) CURRENT (IOL) (mA) AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC
30 25 20 15 10 5
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 7.5 5.0 2.5 10V
10V
5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V 0
FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5
0 -5 -10 -15
0
0 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) 104
-10V
-20 -25
-10V
-10
-15V
-30
-15V
-15
FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS
AMBIENT TEMPERATURE (TA) = +25oC
FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS
DISSIPATION PER INVERTER/BUFFER (PD) (W) 105
8 6 4 2
SUPPLY VOLTAGE (VDD) = 15V 10V 10V 5V CL = 50pF CL = 15pF
OUTPUT VOLTAGE (VO) (V)
SUPPLY VOLTAGE (VDD) = 15V 15
104
8 6 4
10V 10
103
2 8 6 4 2
5V 5
102
8 6 4 2
10
2 4 68
AMBIENT TEMPERATURE (TA) = +25oC
2 4 68 2 4 68 2 4 68
0
5
10 15 INPUT VOLTAGE (VI) (V)
20
25
100
101 102 103 INPUT FREQUENCY (fI) (kHz)
FIGURE 7. TYPICAL VOLTAGE TRANSFER CHARACTERISTICS
FIGURE 8. TYPICAL POWER DISSIPATION AS A FUNCTION OF INPUT FREQUENCY
7-479
CD4502BMS Typical Performance Characteristics
AMBIENT TEMPERATURE (TA) = +25oC TRANSITION TIME (tTHL, tTLH) (ns)
(Continued)
PROPAGATION DELAY TIME (tPLH, tPHL) (ns)
AMBIENT TEMPERATURE (TA) = +25oC
150
SUPPLY VOLTAGE (VDD) = 5V (tTLH) 100 5V (tTLH) 10V (tTLH) 50 15V (tTLH) 10V (tTHL) 15V (tTLH) 0 20 40 60 80 100
250 200 150
SUPPLY VOLTAGE (VDD) = 5V (tPLH)
5V (tPHL) 10V (tPLH)
100 15V (tPLH) 50 10V (tPHL) 15V (tPHL) 0 20 40 60 80 100
LOAD CAPACITANCE (CL) (pF)
LOAD CAPACITANCE (CL) (pF)
FIGURE 9. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE
FIGURE 10. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE
Chip Dimensions and Pad Layout
Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch).
METALLIZATION: PASSIVATION:
Thickness: 11kA - 14kA,
AL.
10.4kA - 15.6kA, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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